Weekly signal for the people building and buying AI infrastructure — what moved, why it matters, what's next.
Memory bandwidth had a big week. Samsung put real numbers on a roadmap that ends with DRAM sitting directly on top of the processor, Micron quantified just how much silicon HBM is eating, and Nvidia is reportedly leaning on all three memory makers to pull forward its next stacking generation. Five stories, one deep dive, one term worth knowing.
Six things that happened this week, and why I'd pay attention to each one.
HBM5 targets 2x HBM4E performance with 20% better performance per watt, moving the base die to a 2nm process, with mass production expected around 2028. A longer-term "zHBM" architecture stacks DRAM directly on the processor, arriving after 2029.
At Hot Chips 2026, Micron said memory now accounts for roughly 90% of the silicon in a two-GPU package, about eight times the area of the GPU dies themselves, as HBM continues to sell for around five times the price of DDR5 per bit.
Nvidia has reportedly asked all three major memory makers to deliver 16-high HBM4 stacks by the fourth quarter, accelerating a timeline that was expected to land closer to HBM4E.
The new instances ship with DDR5-8800 memory, up from DDR5-5600, and 5x the L3 cache of the prior generation, aimed squarely at the memory-bandwidth bottleneck in LLM inference.
30TB enterprise SSDs now list around $22,600, versus $3,460 a year ago. A mixed SSD/HDD 25PB system now costs an estimated $12.86M, versus $51.6M for an all-flash build.
A second major memory vendor is now previewing an HBM alternative aimed at the same processor-to-memory bandwidth gap, promising more than 10x HBM's bandwidth at lower energy per bit.
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A story instead of six headlines, since this roadmap reaches all the way to memory that lives directly on top of the processor.
At Hot Chips 2026, Samsung's DRAM design team, led by Sangwook Han, detailed a three-phase evolution of HBM that gradually moves logic into the base die and, in its final phase, eliminates the 2.5D interposer link between memory and processor entirely. The plan starts with a change Samsung has already made — building the HBM base die on an advanced logic process rather than a memory process — and ends with an architecture the company calls zHBM, where DRAM sits directly on top of the compute die instead of beside it.
The logic behind moving the base die to a logic process first is that it lets Samsung add compute functions — controllers, buffers, eventually more — into the layer that already sits closest to the DRAM stack, without touching the memory cells themselves. That's the foundation the later phases build on. By the time the roadmap reaches zHBM, the 2.5D interposer that currently sits between an accelerator and its HBM stacks disappears altogether, replaced by DRAM stacked directly on the compute die. Samsung says that shortens the distance data has to travel enough to meaningfully improve both bandwidth and power efficiency.
None of this happens quickly. HBM5 alone isn't expected in mass production until around 2028, and zHBM is pegged for after 2029 — which puts it on a similar horizon to the hybrid-bonding transition the industry is already wrestling with (see Issue 03's Deep Cut on HBM's 775-micron packaging ceiling). The two roadmaps are related: hybrid bonding is largely what makes stacking dies directly on top of a processor practical in the first place, so Samsung's zHBM ambitions and the industry's hybrid-bonding timeline are effectively the same race viewed from two different angles.
One piece of storage or memory vocabulary, explained properly, every week.
In plain English: it's a way to fuse two chips directly together, copper-to-copper, without the solder bumps traditional packaging relies on.
Conventional chip stacking uses tiny solder balls, or microbumps, to electrically connect one die to the one below it. Hybrid bonding skips the solder entirely: the copper pads on each die are polished flat and pressed directly together, then annealed with heat until the copper atoms diffuse across the interface and fuse into a single, continuous connection. Because there's no bump sitting between the layers, the dies can be packed far closer together — which matters a lot once you're trying to stack a dozen or more DRAM layers into a fixed thickness budget.
That fixed thickness budget is exactly what Issue 03's Deep Cut covered: HBM stacks are capped around 775 microns to match standard logic wafer thickness, and every additional DRAM layer eats into that ceiling. Hybrid bonding was supposed to be the industry's way past that limit for HBM4E, letting stacks add layers without growing taller. SK hynix's admission that it wasn't ready in time pushed that transition out to HBM5 — which is exactly the generation Samsung's new roadmap (this issue's Deep Cut) is targeting for 2028.
Beyond HBM, hybrid bonding is also the enabling technology behind architectures like Samsung's zHBM, where memory sits directly on top of the processor die rather than beside it on an interposer. Without a bump-free bond, stacking DRAM straight onto a hot, actively switching logic die isn't really practical — the bumps alone would create too much thermal and mechanical stress. So whoever gets hybrid bonding production-ready first isn't just winning a packaging contest; they're unlocking the next tier of memory architecture altogether.
AI Infra Summit 2026, Santa Clara. About as close as this space gets to a dedicated conference. Expect vendors to time announcements around it.
Q3 earnings season for storage and memory vendors (Samsung, SK Hynix, Micron, Western Digital, Seagate). Watch for capex guidance updates and anything on HBM4/HBM5 qualification timelines, given this week's roadmap news.
SC26, Chicago. The HPC/storage world's biggest annual gathering. Parallel file system and interconnect announcements tend to cluster here.